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features adds ir port to standard uart irda, hpsir, ask (cw) & tv remote compatible 1200bps to 115kbps data rate programmable tx led power programmable rx threshold level power down modes direct, no modulation, mode tiny 5x7mm 20 pin ssop package +2.7v to +5.5v supply general description the cs8130 is an infrared transceiver integrated cir- cuit. the receive channel includes on-chip high gain pin diode amplifier, irda, hpsir, ask & tv remote compatible decoder, and data pulse stretcher. the transmit path includes irda, hpsir, ask & tv remote compatible encoder, and led driver. the computer data port is standard uart txd and rxd compatible, and operates from 1200 to 115200 baud. external pin diode and transmit led are required. a control mode is provided to allow easy uart program- ming of different modes. the cs8130 operates from power supplies of +2.7v to +5.5v. ordering information: CS8130-CS 0 to 70 c 20-pin ssop cdb8130 evaluation kit multi-standard infrared transceiver semiconductor corporation this document contains information for a new product. crystal semiconductor reserves the right to modify this product without notice. preliminary product information jun 94 ds134pp2 1 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445-7222 fax: (512) 445-7581 copyright ? crystal semiconductor corporation 1994 (all rights reserved) cs8130 pin diode preamplifier pinc pina threshold detect/decode demodulator uart rxd rxd led driver 1 led1c modulator data/control decoder txd txd dtr baud rate generator xtalout xtalin +supply +supply led driver 2 led2c extclk cts form/bsy reset 6 7 1 4 tgnd2 tgnd1 3 2 clkfr 5 agnd 19 17 18 9 11 10 15 14 16 13 standard fifo va+ 8 +supply vd+ 12 dgnd 20 pwrdn d/c
transmitter driver characteristics (t a = 25 c; all v+ = 3.0v, digital input levels: logic 0 = 0v, logic 1 = v+; unless otherwise specified) parameter symbol min typ max units output capacitance (note 1) 10 tbd pf output rise time (10% to 90%) tr - 20 50 ns output fall time (90% to 10%) tf - 20 50 ns overshoot over final current - - 25 % on resistance - - 0.5 w off leakage current - - 20 m a output current (each driver) (note 2) - - 250 ma output jitter relative a jitter free input clock - - 200 ns notes: 1. typical led junction capacitance is 20pf. 2. 50% duty cycle, max pulse width 165 m s (3/16 of (1/1200 bps + 5%)). specifications are subject to change without notice. receiver characteristics (t a = 25 c; all v+ = 3.0v, digital input levels: logic 0 = 0v, logic 1 = v+; unless otherwise specified) parameter symbol min typ max units input capacitance (note 3) - 10 tbd pf input noise current - - 11 pa/rthz maximum signal input current from detector - - 2 ma maximum dc input current (typically sunlight) - - 200 m a input current detection thresholds rs4-0=00000: (programmable with a 5 bit value) rs4-0=00001: (min, max = typical 30%) rs4-0=00010: (note 4) rs4-0=11110: rs4-0=11111: - - 16.4 169.5 175 7.8 15.6 23.4 242.2 250 - - 30.4 314.9 325 na na na " na na bandpass filter response high pass -3db: low pass -3db: - - 35 700 - - khz khz receiver power up time with high (200 m a) dc ambient with normal (2 m a) dc ambient - - 5 0.3 10 1 ms ms turn-around time, with receiver on continuously (note 5) - 5 10 ms emi rejection of system (0.5mhz to 100mhz). (note 6) 3 - - v/m notes: 3. typical pin diode junction capacitance is 50pf. 4. the 30% tolerance covers chip-to-chip variation. the temperature coefficient of the receiver threshold setting is low. current detection thresholds are above the dc ambient condition. settings of rs4-0 of less than 00010 are not practical because of noise. 5. turn-around time is the time taken for the pin diode receiver to recover from the ir energy from the transmitter. the remote end of the link must wait for this time after receiving data before transmitting a reply. this time may be reduced to <1 ms by good ir shielding from the transmit led to the pin diode. 6. this is a system specification. a metal shield over the pin diode and cs8130 is recommended to ensure system compliance. cs8130 2 ds134pp2
power supply specifications (ta = 25 c; v+ = 3.0v, digital input levels: logic 0 = 0v, logic 1 = v+, note 7) parameter symbol min typ max units power supply voltage 2.7 3.0 5.5 v power supply current - all functions enabled (note 8) - - 2.5 ma power supply current - all functions disabled (note 9) - - 1 m a power supply current - receiver only enabled (note 8) - - 2.5 ma power supply current - transmit only enabled (note 10) - - 0.5 ma oscillator power supply current low power mode: normal power mode: - - - - 0.5 1.5 ma ma data & state retention supply voltage 2 - - v notes: 7. power supply current specifications are with the supply at 3.0v. for approximate consumption at +5.0v, multiply the above currents by 1.667. 8. oscillator in low power mode, does not include led current. subtract oscillator current if using an external clock to run the cs8130. 9. floating digital inputs will not cause the power supply to increase beyond the specification. 10. does not include led current, does include oscillator current in low power mode. recommended operating conditions (all voltages with respect to 0v) parameter symbol min typ max units operating ambient temperature t a 02570 c data and state retention temperature (in power down) -40 - 85 c digital pin characteristics (ta = 25 c, supply = 3.0v) parameter symbol min typ max units high-level input voltage v ih 2.0 - - v low-level input voltage v il --0.8v high-level output voltage at i o = -2.0ma v oh vd-0.3 - - v low-level output voltage at i o = 2.0ma v ol --0.3v output leakage current in hi-z state 0.2 m a input leakage current (digital inputs) - - 0.2 m a output capacitance c out -5-pf input capacitance c in -5-pf cs8130 ds134pp2 3
absolute maximum ratings (all voltages with respect to 0v) parameter symbol min max units power supplies -0.3 6.0 v input current except supply pins & driver pins - 10 ma input voltage -0.3 vd+0.3 v ambient temperature (power applied) -55 +125 c storage temperature -65 +150 c esd using human body model (100pf with series 1.5k w ) 2000 - v warning: operation beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. switching characteristics (t a = 25 c; all v+ = 3.0v, digital input levels: logic 0 = 0v, logic 1 = v+; unless otherwise specified) parameter symbol min typ max units xtalin frequencies clkfr pin low: (note 11) clkfr pin high: - - 3.6864 1.8432 - - mhz mhz xtalin duty cycle 45 50 55 % crystal oscillator start up time - - 25 ms notes: 11. in normal oscillator mode, the crystal is internally loaded with 20 pf, which is the standard loading at which the crystal frequency is tuned. in low power oscillator mode, the internal loading on the crystal is reduced to approximately 5pf. the crystal frequency will therefore increase by about 0.03% in low power mode. cs8130 4 ds134pp2
va+ vd+ agnd pinc pina led1c led2c tgnd1 tgnd2 dgnd clkfr pwrdn d/c txd xtalout xtalin form/bsy rxd cs8130 to led 10 m f +3.0v supply tgnd1, 2 0.1 m f ferrite bead 10 w pin diode 0.1 m f + supply led1 r1 tbd w r2 tbd w rxd cts uart txd dtr system control 3.6864 mhz or 1.8432 mhz. can also use an external clock at 3.6864 mhz or 1.8432 mhz + reset extclk led2 use: led1/r1 or:led1/r1 & r2 or: led1/r1 & led2/r2 for 2 led, +5v supply systems, connect 2 leds in series. use r1 & r2 to give programmable output level. rts + 47 m f clkfr low for 3.6864 mhz clock clkfr high for 1.8432 mhz clock figure 1. recommended connection diagram cs8130 ds134pp2 5
overview the cs8130 is an infrared transceiver i.c. the receive channel includes on-chip high gain pin diode amplifier, irda, hp-sir, 500 khz ampli- tude shift keying (ask) & tv remote compatible decoder, and data pulse stretcher. the transmit path includes irda, hpsir, 500 khz ask & tv remote compatible encoder, and led drivers. the computer data port is standard uart txd and rxd compatible, and operates from 1200 to 115200 baud. an on-chip baud rate generator is provided. external pin diode and transmit led(s) are re- quired. a control mode is provided to allow easy uart programming of different modes. the cs8130 operates from power supplies of +2.7 v to +5.5 v. the device is supplied in a 20- pin ssop package functional description the following pages describe the detailed opera- tion of the cs8130. ir data formats the cs8130 supports three infrared data trans- mission formats: irda/hpsir, 500khz ask and 38khz ask (tv remote). there is also a direct access mode, which bypasses the cs8130 en- coder and decoders, and gives direct access to the ir raw data. this mode is for situations where the encoding and/or decoding is done ex- ternally. modes may be set independently for transmit and receive, although this would be unusual. mode 1 irda/hp-sir the cs8130 is designed to allow easy realiza- tion of an irda compatible ir port (see irda serial infrared (sir) physical layer link speci- fication, version 1.0, april 27 1994). figure 2 shows the format of mode 1. a pulse of ir en- ergy indicates a logic 0. no ir indicates a logic 1. the pulse can be from 3/16 of a bit cell time at 115200 (~1.6 m s), to 3/16 of a bit cell time at 2400 bps (~78 m s). the width of the pulse may be fixed at 1.6 m s for all baud rates, or may scale with the baud rate. the initial baud rate for irda is 9600 bps, with a negotiated baud rate possibility of 2400 to 115200 bps. mode 2 500 khz ask figure 3 shows the infrared data format for mode 2. this is a carrier wave (cw) type sys- tem, where the presence of a 500khz carrier is treated as a 0, and absence of a carrier is treated as a 1. normally used baud rates are 9600 bps, 19.2 kbps and 38.4 kbps. mode 3 38 khz ask (tv remote mode) figure 4 shows the infrared data format for mode 3, the tv remote control mode. this is similar to mode 2, except that the modulation frequency is ~38khz. the ir bit rate is approxi- mately 2400 bps. both modulation frequency and bit rate vary significantly for different manu- facturer and model remote controls. mode 4 direct access mode in mode 4, the ir transmission tracks directly what is present on the txd pin. a logic 1 means that the led is off, a logic 0 means that the led is on. care must be taken to ensure that the led is not on continuously, otherwise the led may be damaged. in mode 4, received ir is compared against the programmed threshold. the resulting logic out- put is routed directly to the rxd pin. a logic 1 means no ir is detected, a logic 0 means ir is being detected. if a ir carrier is being received, cs8130 6 ds134pp2
transmitter txd 10 1 on off * led output pin input light no light receiver ** rxd a b a: 1/baud rate b: 3/16 of 1/115200 o r 3/16 of a (selectable) c: 3/16 of 1/115200 t o 3/16 of a c * led1c and led2c go low to turn on led. ** rxd output is delayed from the pin diode input by a (1 bit). figure 2. infra red data format mode 1 (irda/hpsir) transmitter txd 10 1 on off led output pin input light no light receiver rxd a a: 1/baud rate b: 1/527khz c: 1/500khz +/- 10% c b figure 3. infra red data format mode 2 (500khz ask) transmitter txd data * 10 1 on off led output pin input light no light receiver rxd data * a a: 1/2400 b: 1/38.4khz c: 1/40khz +/- 10% c * the timing of data on the rxd and txd pins is faster than shown here these numbers are typical values. tv remote bit rate and modulation frequency are programmable. b figure 4. infra red data format 3 (tv remote, 38khz ask) cs8130 ds134pp2 7
then the rxd pin will oscillate at the carrier fre- quency. transmit path data for transmission is input to the cs8130 on the txd pin. the selected modulation scheme is then applied to the data, and the resulting signals are used to drive the led. there are 2 led out- put pins: led1c and led2c. they are open drain outputs, which pull down to tgnd or float. the led is connected via resistors to both led1c and led2c. the current level flowing through the led is determined by the external resistors. normally, led1c is used to drive the led. if additional current is needed, (for exam- ple for tv remote operation), then the second driver may be enabled. the amount of boost current is determined by the external resistor connected to the led2c pin. for larger amounts of ir output, it may be pref- erable to use two leds, rather than drive a large current through one led. for a +3v supply sys- tem using two leds, each one is connected, via a resistor, to each driver output. for a +5v sup- ply system, 2 leds may be connected in series, and then routed to each driver via 2 resistors, one for each driver. this minimizes the power dissipation in the resistors. mode 1 transmit choices in mode 1 (irda), the pulse width may be fixed at 1.6 m s, or set to 3/16 of the bit period. either of these settings will meet the irda standard, but fixed 1.6 m s pulses will save power at lower baud rates. in addition, there is a choice which affects the output pulse jitter. the default state causes the cs8130 to look for the start bit on txd. all subsequent led transitions for that character are timed relative to the internal baud rate clock. therefore there will be no jitter in the led out- put pulse timing. however, the cs8130 now has to be programmed with the desired number of bits per character, which for irda compliance, is 8. alternatively, the cs8130 can generate output pulses based entirely on individual transitions on txd, with no knowledge of which bit is the start bit. thus a 1 to 0 transition will generate a pulse based on that transition edge. if txd is low for multiple successive bits, then the cs8130 will generate pulses based on its internal clock. therefore there is the possibility of jitter in the output pulses of n*271 ns. n can be 0, 1 2....., depending on the difference in frequency between the uart baud rate clock and the cs8130 clock. clearly, if the cs8130 and its as- sociated uart are running from the same clock, the possibility of jitter is eliminated. mode 2 (ask) transmit choices the modulation frequency is determined by the modulator divider registers. for nominal 500 khz, use a divide value of 6, which yields a modulation frequency of 527 khz. mode 3 (tv remote) transmit choices during transmission of ir, the start and stop bits present in the incoming data from the uart are stripped off (see figure 5). the remaining data bits are then sent out at ~2400 bps. since there should be no gaps in the transmitted data, the input data is buffered in a 22-character location fifo. characters can be received on the txd pin while the previous characters are being trans- mitted. to prevent overflow, a hardware handshake mechanism is provided. if the fifo is one character away from being full, the form/bsy pin is brought high, indicating that the uart should not send any more data. once another character has been transmitted, form/bsy pin is brought low, indicating to the uart that it is ok to send another character. cs8130 8 ds134pp2
the modulation frequency is determined by the modulator divider registers. the transmit bit rate is determined by the tv remote transmit bit rate divider. the uart to cs8130 baud rate must be set to at least 20% faster than the transmit bit rate. receive path a pin diode is attached to the pina and pinc pins. compensation for the dc ambient light is applied to the photocurrent from the diode. the change in photocurrent from ambient is ampli- fied and compared to a threshold value. if the photocurrent is greater than the set threshold, the output is set to light. if the photocurrent is less than the set threshold, the output is set to no light. the threshold current is programmable. this allows users to make the tradeoff between noise immunity and the reliable transmission dis- tance of the link. the pin diode amplifier has a bandpass filter characteristic, to limit the effects of ir interference. the resulting logic signal is further qualified, depending on the ir format se- lected. an autodetect feature is provided. if autodetect mode is enabled, and transmit tv remote mode is disabled, the form/bsy output pin indicates the format of incoming data. if high, then the incoming data is in irda/hpsir format. if low, the data is in ask format which matches the programmed modulation frequency. mode 1 (irda) receive choices for mode 1a, a logic circuit is set to only look for pulse widths of 1.6 m s. for mode 1b, a logic circuit looks for pulses of 3/16 of the set baud rate bit period. for mode 1c, a logic circuit looks for pulse widths of 3 1.6 m s, but 3/16 of the set baud rate bit period. mode 2 (ask) receive choices for mode 2, a logic circuit looks for sequences of light and no light which matches the ex- pected 500khz carrier. the modulator divider registers must be set to 6. the ask receive tim- ing sensitivity register should be set to 0, yielding a valid incoming frequency range of 461 khz to 614 khz. the rxd data transitions will lag behind the in- frared activity by 3 modulation cycles. this allows the modulation detect circuit time to ver- ify the correct modulation frequency. 10 11 00 01 10 10 001 001 1 000 1 start bit stop bit a bc 1/2400 1 1 abc on off * txd baud rate can be set from 4800 to 115200 bps led output form/bsy txd* txd* figure 5. mode 3 (tv remote) transmit data format cs8130 ds134pp2 9
mode 3 (tv remote) receive choices the modulation frequency must be set into the modulator divider registers. the tolerance on the expected frequency must be programmed into the receive ask timing sensitivity (rats) reg- ister. the rats register sets the time window that the demodulator will accept for the period of valid data. since the rats register specifies time windows which are negative (e.g. 1000b (8) = +0.27 m s to -4.61 m s), then the modulation frequency must be set to lower than the desired nominal setting. for example, with rats set to 1000 (8), and the desired nominal frequency be- ing 38 khz, then set the modulation divider registers to 35.10 khz. with these settings, the demodulator will accept any frequency from 34.78 khz to 41.88 khz as valid. smaller rats register settings will result in tighter tolerance on the accepted receive modulation frequency. changes in the rats register settings must be accompanied by changes in the modulation fre- quency register to keep the nominal desired frequency in the center of the valid frequency band. there are two tv remote receive data modes: "oversampled" mode and "programmed t pe- riod" mode. for "oversampled" mode, first choose the uart to cs8130 baud rate, typically 115.2 kbps. then set the tv remote receive tim- ing register to a rate which is less than 80% of the uart baud rate. the cs8130 will now start sampling the demodulated infrared data at the tv remote receive sample rate. the stream of samples will be assembled into characters, with a start bit and a stop bit, and will be transmitted to the uart via rxd at the uart baud rate. the system software can then concatenate successive characters and reconstruct the incoming bit stream. "programmed t period" mode requires that the bit period of the bursts of modulated carrier be known. this period is programmed into the tv remote receive timing registers. the uart to cs8130 baud rate must be set to at least 20% greater than 1/t. the cs8130 will now use the edges of the demodulated incoming infrared data to indicate each bit state. for continuous periods of low or high, the cs8130 will sample the level in the center of each incoming bit period (using t as the bit period). any transition will reset the timer that is used for the sampling process, thereby eliminating errors caused by the sample timing being different to the incoming bit period. characters are assembled and sent to the uart every 8 bits (see figure 6). if the t period is not known, it is possible to measure t by using "oversampled" mode, and 1 0 1 1 00 1 110 0 11 0 01 1 0 0 1 01 1 00 1 1 1/2400 light input rxd* rxd* light no light stop bit 8 data bits start bit *rxd baud rate can be set from 4800 to 115200 bps figure 6. mode 3 (tv remote) receive data format cs8130 10 ds134pp2
then switch to "programmed t period" mode to reduce processing overhead in the host cpu. clock generation the primary clock required is 3.6864 mhz. this may be generated by attaching a 3.6864 mhz crystal to the xtalin and xtalout pins. in this case, the extclk pin becomes an output, and may be used to drive external devices. if this is not required, power may be saved by disabling the extclk output. the clkfr pin should be connected to dgnd, which causes the clock cir- cuits to be configured for 3.6864 mhz operation. the oscillator has a low power mode. this re- duces the internal crystal loading capacitance on xtalout and xtalin. the selection of this mode is via a bit in control register #4. since the loading capacitance is reduced, then the crys- tal frequency will increase by approximately 0.03%. alternatively, a 3.6864 mhz clock may be input into the extclk pin, in which case xtalin must be grounded, and xtalout is left float- ing. the clkfr pin must be connected to dgnd. if only a 1.8432 mhz clock is available, then it may be input into the extclk pin and the clkfr pin connected to vd+. this causes the cs8130 to double the incoming 1.8432 mhz clock to 3.6864 mhz for internal use. xtalin must be grounded, and the xtalout pin is left floating. the cs8130 automatically sets the direction of the extclk pin. if the crystal oscillator is run- ning when reset goes high, then extclk becomes an output. since the crystal oscillator can take up to 25 ms to start, then it follows that reset must be held low, with pwrdn high and power applied, for at least 25 ms. if using an external clock, then reset low can be short (>1 m s). power down when the pwrdn pin is brought low, all inter- nal logic is stopped, including the crystal oscillator. the power consumption in power down mode is very low (<1 m a). when the pwrdn pin is brought high, the crystal oscilla- tor will start. if using the crystal oscillator, allow 25 ms for oscillator start up after bringing pwrdn high, before trying to use the cs8130. the control register status will not be changed by toggling pwrdn. control register #1 allows for individual dis- abling and enabling of the transmit and receive sections of the cs8130. the cs8130 also goes into power down if both transmit enable and receive enable bits are false, and the d/ c pin is brought high. this allows control of power down in a pod environment, where access to the pwrdn pin is difficult. in this mode, it is possible to select, via a control register bit, whether the crystal oscillator remains running, or is powered off. if the oscillator re- mains running, then it consumes power, but offers instant wake up. if the oscillator is pow- ered off, then it consumes no power, but will take 25 ms to start up. the pwrdn pin must always be high or low. if this pin is allowed to float, excessive power consumption may occur. all other digital inputs may be allowed to float without causing excessive power consumption in the cs8130 in power down mode. the rxd and form/bsy output pins may be programmed to be high, low or float in power down. this allows maximum flexibility in differ- ent applications. cs8130 ds134pp2 11
reset bringing the reset pin low will force the inter- nal logic, including the control registers, into a known state, provided the pwrdn pin is high. reset is disabled if the pwrdn pin is low. the reset state is given in each register definition table. reset must be low for >25 ms if using the crystal oscillator (see clock generation above). control register definitions the various control registers within the cs8130 may be written by setting the d/ c pin to low, and sending characters from the uart to the txd pin. the characters are interpreted as a 4- bit address field and a 4-bit data field, as shown in figure 7. after the control character is re- ceived and written into the control register, it is optionally echoed back out the rxd pin. the baud rate used for this control mode is whatever is currently set in the baud rate register. if the "load baud rate" bit is written to, then the new baud rate takes effect after the character has been echoed back, if echo is enabled. otherwise, the new baud rate is effective immediately. one of the control registers contains a shadow register set enable bit, which effectively becomes the msb of the 5-bit register address. hence there are 31 4-bit registers. the shadow bit must be written to a 1 to allow access to the registers with addresses 16 through 31. the shadow bit register is always accessible, independent of the state of the shadow bit. the shadow bit must be written to 0 to enable access to registers 0 through 15. the following tables define the detailed function of all the registers inside the cs8130. cd0 cd1 cd2 cd3 ad0 ad1 ad2 ad3 cd0 cd1 cd2 cd3 ad0 ad1 ad2 ad3 start bit data address stop bit start bit data address stop bit txd d/c rxd figure 7. control mode timing cs8130 12 ds134pp2
bit name value function ad3-0 register address (4 bits of transmitted address + msb, which is the shadow (shdw) bit state [control reg #3]. all registers have 4 data bits). 0_0000 0_0001 0_0010 0_0011 0_0100 0_0101 0_0110 0_0111 0_1000 0_1001 0_1010 0_1011 0_1100 0_1101 0_1110 0_1111 1_0000 1_0001 1_0010 1_0011 1_0100 1_0101 1_0110 1_0111 1_1000 1_1001 1_1010 1_1011 1_1100 1_1101 1_1110 1_1111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 control register #1 control register #2 transmit mode register #1 transmit mode register #2 output power register receive mode register receive sensitivity register #1 receive sensitivity register #2 baud rate divider register #1 baud rate divider register #2 modulator divider register #1 modulator divider register #2 digital output pin control register control register #3 reserved status register (read only) tv remote receive sample rate & t period divider tv remote receive sample rate & t period divider tv remote receive sample rate & t period divider tv remote transmit bit rate divider #1 tv remote transmit bit rate divider #2 control register #4 reserved reserved ask receive timing sensitivity register reserved reserved reserved cs8130 revision level register (read only) reserved reserved (resets to 1111; must not be c hanged) reserved (resets to 1111; must not be c hanged) cd3-0 control data contains control register data. it is essential that all reserved registers and bits are not changed from their reset state. if reserved bits are changed, then internal test modes may be invoked, which may change some input pins to output pins, and may completely change the definition of some functions and signals. reserved bits in regis- ters, and reserved registers, may not return a known state when read, and should be ignored. registers 28 and 15 are read only. other non-reserved registers are write only. the cs8130 can be set to echo back register write commands to verify correct reception of the control settings. control data byte format d7 d6 d5 d4 d3 d2 d1 d0 ad3 ad2 ad1 ad0 cd3 cd2 cd1 cd0 cs8130 ds134pp2 13
register 0, control register #1 d3 d2 d1 d0 echo 0 rxen txen 0000 register reset (r) bit name value function echo echo control characters 0 1 r do not echo control characters echo control characters. rxen receiver enable 0 1 r receiver disabled receiver enabled txen transmitter enable 0 1 r transmitter disbabled transmitter enabled register 1, control register #2 d3 d2 d1 d0 0 0 autd lodb 0000 register reset (r) bit name value function autd receiver auto detect mode enable 0 1 r auto detect receive format disabled auto detect receive format enabled lodb load baud rate counter 0 1 r do not load new baud rate count value load new baud rate count value the lodb bit resets to 0 automatically. cs8130 14 ds134pp2
register 2, transmit mode register #1 d3 d2 d1 d0 dir tvr pwid modu 0000 register reset (r) bit name value function dir direct mode enable 0 1 r mode 4 direct access mode disabled mode 4 direct access mode enabled tvr tv remote mode enable 0 1 r mode 3 tv remote mode disabled mode 3 tv remote mode enabled pwid select pulse width 0 1 r set pulse width to 1.6 m s set pulse width to 3/16 of the bit period modu select modulation method 0 1 r mode 1 irda pulse modulation enabled mode 2 amplitude modulated carrier modulation register 4, output power register d3 d2 d1 d0 00op1op0 0000 register reset (r) bit name value function op1-0 output power level 00 01 10 11 0r 1 2 3 no led output enabled led1c output only enabled led2c output only enabled both led1c and led2c outputs enabled register 3, transmit mode register #2 d3 d2 d1 d0 0 chsy bc1 bc0 0110 register reset (r) bit name value function chsy character/bit synchronized 0 1r bits are transmitted based on txd bit transitions bits are transmitted timed from the start bit bc1-0 number of bits per character (only needed if chsy = 1) 00 01 10 11 0 1 2r 3 6 data bits per character 7 data bits per character 8 data bits per character 9 data bits ( 8 data, 1 parity) per character cs8130 ds134pp2 15
register 5, receive mode register d3 d2 d1 d0 rtvr rmod rwids rwidl 0011 register reset (r) bit name value function rtvr, rmod, rwids, rwidl receive mode 0000 0001 0010 0011 0100 1000 1100 0 1 2 3r 4 8 12 mode 2 amplitude modulated carrier mode mode 1a irda - fixed 1.6 m s pulse mode 1b irda - variable 3/16 bit cell time pulse mode 1c irda - any width pulse from 1.6 m s to 3/16 bit cell time mode 4 direct access mode mode 3 tv remote mode, oversampling receive mode 3 tv remote mode, timed bit cell receive all other combinations are reserved register 6, receive sensitivity register #1 d3 d2 d1 d0 rs3 rs2 rs1 rs0 0111 register reset (r) bit name value function rs4-0 receive threshold setting. 00000 00001 " 00111 " 11110 11111 0 1 " 7r " 30 31 7.8 na nominal receive threshold 15.6 na nominal receive threshold " 62.5 na nominal receive threshold " 242.2 na nominal receive threshold 250 na nominal receive threshold threshold settings of less than 20na should not be used because background noise will cause the apparent occurrence of constant signal. register 7, receive sensitivity register #2 d3 d2 d1 d0 000rs4 0000 register reset (r) cs8130 16 ds134pp2
register 8, baud rate divider register #1 d3 d2 d1 d0 br3 br2 br1 br0 0111 register reset (r) bit name value function br7-0 baud rate divider value (brd). brd=(3.6864e6/ (16*br))-1, where brd = divider value and br = desired baud rate. 01011111 0010 1111 00010111 00001011 00001001 00000010 00000001 95 47 23 r 11 5 2 1 2400 bps 4800 bps 9600 bps 19.2 kbps 38.4 kbps 76.8 kbps 115.2 kbps register 9, baud rate divider register #2 d3 d2 d1 d0 br7 br6 br5 br4 0001 register reset (r) register 10, modulator divider register #1 d3 d2 d1 d0 md3 md2 md1 md0 0110 register reset (r) bit name value function md7-0 modulator divider value (md). md=(3.6864e6/fr)- 1, where md = divider value and fr = desired modulation frequency. 01100000 00000110 96 6r 38 khz 527khz the transmitted modulation frequency will be exact. the receive carrier detection frequency can be slightly different from the programmed frequency (see receive ask carrier timing register). register 11, modulator divider register #2 d3 d2 d1 d0 md7 md6 md5 md4 0000 register reset (r) cs8130 ds134pp2 17
register 15, status register d3 d2 d1 d0 0 oscr err dmod 000 register reset (r) bit name value function oscr oscillator running flag 0 1 oscillator not running, using external clock input, oscillator circuit is powered down. oscillator running, extclk is an output, if enabled. err framing error flag 0 1 r no error a framing error has occurred since the last read of this bit. resets after read dmod detected modulation type 0 1 r irda pulse style data format detected amplitude modulated carrier style data format detected to read this register, write 0000 to address 15. independent of the setting of the echo bit, the cs8130 will transmit the above contents, with an address field of 1111. register 12, output pin control register d3 d2 d1 d0 rxdt rxdh fort forh 0101 register reset (r) bit name value function rxdt rxd output pin three-state enable 0 1 r in power down, rxd will go high or low. in power down, rxd will float. rxdh rxd output pin high/low enable 0 1r in power down, rxd will go low, if rxdt = 0 in power down, rxd will go high, if rxdt = 0 fort form/bsy output pin three-state enable 0 1 r in power down, form/bsy will go high or low. in power down, form/bsy will float. forh form/bsy output pin high/low enable 0 1r in power down, form/bsy will go low, if fort = 0 in power down, form/bsy will go high, if fort = 0 register 13, control register #3 d3 d2 d1 d0 0 0 0 shdw 0000 register reset (r) bit name value function shdw shadow register set enable 0 1 r enable access to registers 0 though 15 enable access to shadow registers (16 through 31) cs8130 18 ds134pp2
register 16, tv remote receive timing register #1 d3 d2 d1 d0 tvr3 tvr2 tvr1 tvr0 1111 register reset (r) bit name value function tvr11-0 tv remote mode receiver timing register tvr = (3.6864e6 * t) -1 where t = the incoming bit period, and tvr = this register value. 000000000000 000000000001 011111111111 111111111111 0 1 2047r 4095 t = 271 ns t = 542 ns t = 555 m s (1800 bps) t = 1.11 ms for tv remote receive "oversampled" mode, this register value determines the input data sample rate. the sample rate is 3.6864 mhz divided by this register value. the sample rate should be set to as fast as possible, to give the best resolution on the incoming data edges, but should be less than 80% of the main uart communication baud rate. for tv remote receive "programmed t period" mode, this register sets the expected incoming bit cell time (t). the main uart communications rate must be set to at least 20% greater than 1/t. register 17, tv remote receive timing register #2 d3 d2 d1 d0 tvr7 tvr6 tvr5 tvr4 1111 register reset (r) register 18, tv remote receive timing register #3 d3 d2 d1 d0 tvr11 tvr10 tvr9 tvr8 0111 register reset (r) cs8130 ds134pp2 19
register 19, tv remote transmit bit rate divider register #1 d3 d2 d1 d0 tbr3 tbr2 tbr1 tbr0 1111 register reset (r) bit name value function tbr7-0 tv remote mode transmit bit rate register tbr= (3.6864e6/(16*rate)) -1 where tbr is this register value & rate is the desired transmit bit rate. 01111111 127 r rate = 1800 bps register 20, tv remote transmit bit rate divider register #2 d3 d2 d1 d0 tbr7 tbr6 tbr5 tbr4 0111 register reset (r) register 21, control register #4 d3 d2 d1 d0 osce oscl exck sres 0000 register reset (r) bit name value function osce disable crystal oscillator in d/ c controlled power down state 0 1 rin d/ c controlled power down state, crystal oscillator stays running. in d/ c controlled power down state, crystal oscillator stops. oscl set oscillator in low power mode 0 1 r oscillator in normal power, high accuracy, mode. oscillator in low power, medium accuracy mode. exck disable external clock output driver 0 1 r if crystal is used, enable clock output driver if crystal is used, disable clock output driver (hi-z) sres software reset 0 1 r normal operation causes a software reset, which forces all registers into their reset state. if echo is true, then the echo will occur at the current baud rate, before the baud rate changes to the default value. cs8130 20 ds134pp2
register 28, cs8130 silicon revision register d3 d2 d1 d0 rev3 rev2 rev1 rev0 register bit name value function rev3-0 cs8130 silicon revision level 0000 1st silicon, designed to meet ds134pp2 data sheet, dated june 1994 this register should be read by the cs8130 driver to allow cs8130 future enhancements to be recog- nized, and incorporated into future versions of the driver. register 24, receive ask timing sensitivity register d3 d2 d1 d0 rat3 rat2 rat1 rat0 0000 register reset (r) bit name value function rat3-0 receiver ask timing sensitivity. timing window = +0.27 m s to -rat(2/3.6864e06) - 0.27 m s 0000 0001 0010 1111 0r 1 2 15 +0.27 m s to -0.27 m s window (500 khz ask mode) +0.27 m s to -0.54 - 0.27 m s window +0.27 m s to -1.08 - 0.27 m s window +0.27 m s to -8.14 - 0.27 m s window the timing window is relative to the modulation divider register nominal setting. cs8130 ds134pp2 21
grounding & layout grounding and layout for the cs8130 are criti- cal, because of the sensitive nature of the pin diode amplifier. the cs8130 should be over its own dedicated ground plane. the pin diode should be very close to the pina and pinc pins. the pin diode traces should be very short (< 5 mm), and should be surrounded by ground plane. there should be holes in the ground plane provided for mounting a metal shield over the cs8130 and the pin diode for emi shielding. the pin diode and transmit leds should be po- sitioned so as to line up the front optical surfaces of the packages. the optical surface of the pin diode and transmit led(s) should be positioned 1cm back from the daylight ir filter window in- side the case of the equipment. this ensures that direct sunlight does not fall upon the top surface of the pin diode. an evaluation kit, cdb8130, is available from crystal. this may be used as an example of the correct layout for the cs8130 and the optical components. optical components temic (tel: 408 970 5684) provides telefunken infrared leds and pin diodes which are com- patible with the cs8130. contact crystal for details of additional qualified led and pin di- ode sources. example application schematics crystal has prepared some example schematics which demonstrate possible uses for the cs8130. figure 8 shows a computer or pda motherboard example, where one uart is used to drive both a wired rs232 com port and an ir port. figure 9 shows a pod schematic. this is an ex- ternal unit which can be plugged into any existing com port to create an ir port. schematic & layout review service confirm optimum schematic & layout before building your board. for our free review service call applications engineering. call: (512) 445-7222 cs8130 22 ds134pp2
va+ vd+ agnd pinc pina led1c led2c reset tgnd1 tgnd2 dgnd extclk xtalin xtalout rxd form/bsy txd d/c pwrdn clkfr 812 5 7 6 1 4 19 17 18 13 16 14 15 10 9 2 320 0.1 m f + 10 m f +3v 0.1 m f + 10 m f + 47 m f +3v 10 w 5.2 w (2) 5.2 w (2) 3.6864 mhz cs8130 bpv23nf tsha5502 cia- cia+ max562 vcc cib- cib+ t1out t2out r1in r2in v- v+ gnd 27 28 26 3 4 1 5 2 0.33 m f +3v 0.33 m f 0.33 m f c2+ c2- 24 25 0.33 m f 0.68 m f 0.33 m f 5 20 21 22 23 dtr db9 serial connector (com port) r1out r2out r3out r5out r4out en shdn 15 14 r3in r4in r5in t3out t2in t1in t3in 16 17 18 19 9 8 7 6 13 12 11 10 rts txd rxd dcd ri dsr cts 6 8 2 1 9 4 7 3 dtr rts txd rxd dcd ri dsr cts sg uart rs-232/ir select 11 notes: (1) this circuit has not yet been built and debugged. (2) choice of led, power consumption and physical positioning will affect r value. uart to both rs232 and ir port interface motherboard example schematic steven harris crystal semiconductor 5/26/94 figure 8. ir and rs232 from 1 uart cs8130 ds134pp2 23
va+ vd+ agnd pinc pina led1c led2c reset tgnd1 tgnd2 dgnd extclk xtalin xtalout rxd form/bsy txd d/c pwrdn clkfr 812 5 7 6 1 4 11 19 17 18 13 16 14 15 10 9 2 320 0.1 m f + 10 m f +3v 0.1 m f + 10 m f + 47 m f +3v 10 w 5.5 w (2) 5.5 w (2) +3v 3.6864 mhz 15 en shdn +3v cia- cia+ t1in t2in r1out r2out cs8130 max562 vcc cib- cib+ t1out t2out r1in r2in v- v+ gnd 27 28 26 22 23 17 18 3 4 1 5 2 11 12 6 7 0.33 m f +3v 0.33 m f 0.33 m f c2+ c2- 24 25 0.33 m f 0.68 m f 0.33 m f 5 4 3 8 2 rxd cts txd dtr db9 serial connector (com port) bpv23nf tsha5502 rs232 com port to infra red interface pod schematic steven harris crystal semiconductor 5/26/94 14 notes: (1) this circuit has not yet been built and debugged. (2) choice of led, power consumption and physical positioning will affect r value. (3) the creation of +3v or +5v supply is not included here. r3in 21 7 rts r3out 8 figure 9. example pod schematic cs8130 24 ds134pp2
power supplies vd+ - digital positive supply. digital positive supply voltage. nominally +3v va+ - analog positive supply. analog positive supply voltage. nominally +3v. dgnd - digital ground. digital ground, 0v, connection. agnd - analog ground. analog ground, 0v, connection. tgnd1, tgnd2 - transmitter grounds. led transmitter grounds, 0v, connections. analog pins led1c, led2c - transmit led cathode. these pins are connected to the transmit led cathode via resistors. appropriate resistor choice allows user setting of led current options. the anode of the led is connected to the positive supply. pinc - receiver pin diode cathode receiver pin diode cathode. pina - receiver pin diode anode. receiver pin diode anode. led1 cathode led1c dgnd digital ground transmit ground 1 tgnd1 extclk external clock transmit ground 2 tgnd2 xtalou t crystal output led2 cathode led2c xtalin crystal input analog ground agnd form/bsy format/busy pin diode anode pina d/ c data/control pin diode cathode pinc txd transmit data analog supply va+ rxd receive data clock frequency clkfr vd+ digital supply power down pwrdn reset reset 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 cs8130 ds134pp2 25
digital pins rxd - receiver data output receiver output data. normally connected to rxd on the uart. txd - transmit data input transmitter input data. normally connected to txd on the uart. d/ c - data/control mode input the d/ c pin determines whether the input data on txd is treated as data to be transmitted via the led, or as control information to set up the cs8130 internal registers. the d/ c pin also can act as a power down control. form/bsy - received data format output/busy signal output if auto format detect mode is enabled, this pin indicates the format of the incoming data. form is low for ask format data, and high for irda/hpsir format data. in tv remote data mode (mode 3), this pin becomes a handshake signal to the uart. form/bsy low means ok to send a character. form/bsy high means "i am busy, do not send another character". pwrdn - power down control input pwrdn low places the cs8130 into a very low power consumption "off" state. reset - reset input reset low places all the internal logic into a known state. all the control register bits are forced high or low, as defined in the register definition section. if the crystal oscillator is in use, then reset must be held low for >25 ms, with pwrdn high and power applied. if an external clock is used, then the reset pulse can be short (>1 m s). xtalin, xtalout - crystal connections to use the internal oscillator, connect either a 3.6864 mhz or a 1.8432 mhz crystal between xtalout and xtalin. if using an external clock, connect xtalin to dgnd. extclk - external clock input or output if no crystal is present on xtalin and xtalout, extclk becomes an input. a 3.6864 mhz or 1.8432 mhz clock should be connected to extclk. xtalin should be connected to dgnd. if a crystal is present on xtalin and xtalout, extclk becomes an output. extclk will output the same frequency as the crystal. the extclk output driver may be disabled to conserve power. clkfr - clock frequency select input tie clkfr to ground to select a 3.6864 mhz clock. connect clkfr to the vd+ pin to select a 1.8432 mhz clock. cs8130 26 ds134pp2
44 20 pin ssop 28 pin ssop e a a d e a 1 1 s i d e v i e w e n d v i e w t o p v i e w seating plane n o t e s : 1. "d" and "e " are reference datums and do not include mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25mm from lead tips. n 13 2 ssop package dimensions n millimeters min nom max 20 28 6.90 7.20 7.50 9.90 10.20 10.50 note 1 1 1 2 1 dim millimeters min nom max a a a b d e e e l n - - 2.13 0.05 0.15 0.25 1.62 1.75 1.88 0.22 0.30 0.38 see other table 5.00 5.30 5.60 7.40 7.80 8.20 0.63 0.90 1.03 see other table 0 4 8 note 2, 3 1 1 1 2 1 e b 2 0.61 0.65 0.69 l inches min nom max - - 0.084 0.002 0.006 0.010 0.064 0.070 0.074 0.009 0.012 0.015 see other table 0.197 0.209 0.220 0.291 0.307 0.323 0.025 0.035 0.040 see other table 0 4 8 0.024 0.026 0.027 d inches min nom max 0.272 0.283 0.295 0.390 0.402 0.413 1
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